PlantUML Web Server

@startuml
skinparam linetype ortho

hide stereotype
<style>

.application_layer {
  BackgroundColor #DBE8FF
  LineColor #778FB2
}

.widthcontrol {
  MinimumWidth 20
  BackgroundColor palegreen
  LineColor palegreen
  FontColor palegreen

}

.rte {
  BackgroundColor #FFE7CD
  LineColor Orange
  MinimumWidth 350
  LineThickness 1
  HorizontalAlignment center
  RoundCorner 0
}

.basic_software {
  BackgroundColor #E1D5E7
  LineColor blue
  MinimumWidth 800 'ignored
  RoundCorner 0
  LineThickness 1
  HorizontalAlignment right 'ignored
}

.nvm {
  BackgroundColor #DBE8FF
  LineColor #778FB2
  MinimumWidth 200
  LineThickness 2
  HorizontalAlignment center
}

.bus_tp {
  BackgroundColor #FFE7CD
  LineColor Orange
  RoundCorner 60
  LineThickness 2
  HorizontalAlignment right
}

.mcal {
  BackgroundColor #F9CECD
  LineColor #A2585C
  RoundCorner 60
  LineThickness 2
  HorizontalAlignment right 'ignored
}

.memif {
  BackgroundColor #D6E9D5
  LineColor #92AC71
  MinimumWidth 200
  LineThickness 2
  HorizontalAlignment center
}

.minor {
  BackgroundColor #F7F7F7
  LineColor #626765
  MinimumWidth 50
  LineThickness 2
  HorizontalAlignment center
}

.hardware {
  BackgroundColor #FFF2CC
  LineColor #D0B870
  MinimumWidth 50
  LineThickness 2
  HorizontalAlignment center
}

</style>

rectangle "                                     Application Layer" as application <<application_layer>> {
  'rectangle widthcontrol1 <<widthcontrol>>
  rectangle "\nSW-C\n" as swc
  'rectangle widthcontrol2 <<widthcontrol>>
}

rectangle RTE <<rte>>
swc --> RTE
RTE -[norank]-> swc
application -[hidden]-> RTE

rectangle "                                              Basic Software" <<basic_software>> {
  rectangle "NvM" <<nvm>>
  rectangle "BusTP" <<bus_tp>> {
    rectangle Memif <<memif>>
    rectangle EA <<minor>>
    rectangle FEE <<minor>>
    Memif --> EA
    EA -[norank]-> Memif
    Memif --> FEE
    FEE -[norank]-> Memif  
  }
  rectangle Mcal <<mcal>> {
    rectangle EEP <<minor>>
    rectangle FLS <<minor>>
  }
NvM --> Memif
Memif --> NvM
EA --> EEP
EEP --> EA
FEE --> FLS
FLS --> FEE
}
rectangle "                                                     Hardware" as Hardware <<hardware>> {
rectangle EPROM <<minor>>
rectangle Flash <<minor>>
}

RTE --> NvM
NvM -[norank]-> RTE

EEP --> EPROM
EPROM -[norank]-> EEP

FLS --> Flash
Flash -[norank]-> FLS

Mcal -[hidden]-> Hardware
@enduml

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