RTL9310 Clock tree Ref CLK (25 MHz) OCP PLL (500 ~ 1000 MHz) DIV (1, 2, 4) CPU clock (125 ~ 1000 MHz) MEM PLL (250 ~ 800 MHz) Memory Controller DIV (DFI) (MAC:PHY 1:2 ratio) DDR clock (250 ~ 800 MHz or fixed 100 MHz) GPHY (25 MHz) SerDes (25 MHz) SWCore PLL (1.2 ~ 1.6 GHz)? DIV (6, 8, 10, 12)? LeXra bus (200 MHz max) USB 2.0 (internal PLL (30 MHz) SPI-NAND (200 MHz max) DIV (2, 4, 6, ... 16) SPI NAND clock (100 MHz max) DIV (6, 8, 10, 12)? SPI-NOR (200 Mhz max) DIV (2, 4, 6, ..., 16) SPI NOR Flash clock (100 Mhz max)